FPGA and ASIC IP CORES

The mainstream consumer and professional video applications use highly optimized, specialized hardware to perform video encoding and decoding. While PC software SDKs are most flexible to integrate and take less time to optimize, hardware codecs excel in high volume and high density implementations due to their lower power usage and lower overall platform cost. Most familiar brands of consumer and professionals cameras, TVs, broadcast and video communication equipment rely on hardware codec OEM suppliers. The big challenge for such suppliers is the high cost and lengthy time of hardware codec development. Few competitors are able to succeed in this highly competitive market. Many years of codec optimization experience on variety of FPGA, DSP and ASIC platforms enables VSS to succeed where many have failed. VSS development strategy always starts with development of algorithms and video coding tools which are the essential starting point for any hardware codec. VSS FPGA IP core development success is based on:

• Starting with fully developed algorithms, available as C-model code
• Modular architecture with pipeline communication between components
• Easy optimization for verity of FPGA devices, resulting in balance of great video quality with least FPGA resources
• Adaptation of multiple applications from ultra-low latency for communication to ultra-high efficiency of live broadcast.