H.264 CABAC Decoder

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VSofts H.264 CABAC Decoder IP core is a platform-agnostic (VHDL) design for hardware acceleration of the CABAC entropy decoder. The design supports the H.264 Main Profile (excluding MBAFF) and is portable to ASIC and FPGA elements.

Context-adaptive binary arithmetic coding (CABAC) is the most efficient entropy coding scheme used in the H.264/AVC standard. It is the first stage in video decompression, and is one of the most processor-intensive parts of the process. The serial data stream is the bottleneck of CABAC processing, and makes ordinary processors ineffective in this task. The IP core provides the design for an effective bit-oriented co-processor to significantly speed up CABAC performance.

Features

• H.264 Main Profile support (excluding MBAFF)
• Optimized for Xilinx and Altera FPGAs
• Up to HD resolution (1920x1088)
• 4:2:2 and 4:4:4 sampling
• 8 bit and 10 bit sampling
• Low gate and memory requirements
• Excellent performance at ~1.5 cycles per input bit, up to 80 MHz
• Easy integration via input and output FIFOs

Includes

• C software model
• VHDL source code or binary IDEF file
• Technical documentation
• Test bench source code
• Test vectors
• Integration support and after-sale support